switchmode series npn silicon power transistor the mj13333 transistor is designed for high voltage, highspeed, power switching in inductive circuits where fall time is critical. it is particularly suited for line operated switchmode applications such as: ? switching regulators ? inverters ? solenoid and relay drivers ? motor controls ? deflection circuits ? fast turn off times 200 ns inductive fall time e 25 c (typ) 1.8 m s inductive storage time e 25 c (typ) ? operating temperature range 65 to +200 c ? 100 c performance specified for: reversed biased soa with inductive loads switching times with inductive loads saturation voltages leakage currents ????????????????????????????????? ????????????????????????????????? maximum ratings ????????????????????? ????????????????????? rating ????? ????? symbol ?????? ?????? value ???? ???? unit ????????????????????? ????????????????????? collectoremitter voltage ????? ????? v ceo ?????? ?????? 400 ???? ???? vdc ????????????????????? ????????????????????? collectoremitter voltage ????? ????? v cev ?????? ?????? 700 ???? ???? vdc ????????????????????? ????????????????????? emitter base voltage ????? ????? v eb ?????? ?????? 6.0 ???? ???? vdc ????????????????????? ? ??????????????????? ? ????????????????????? collector current e continuous peak (1) ????? ? ??? ? ????? i c i cm ?????? ? ???? ? ?????? 20 30 ???? ? ?? ? ???? adc ????????????????????? ????????????????????? base current e continuous peak (1) ????? ????? i b i bm ?????? ?????? 10 15 ???? ???? adc ????????????????????? ? ??????????????????? ? ? ??????????????????? ? ????????????????????? total power dissipation @ t c = 25 c @ t c = 100 c derate above 25 c ????? ? ??? ? ? ??? ? ????? p d ?????? ? ???? ? ? ???? ? ?????? 175 100 1.0 ???? ? ?? ? ? ?? ? ???? watts w/ c ????????????????????? ????????????????????? operating and storage junction temperature range ????? ????? t j , t stg ?????? ?????? 65 to +200 ???? ???? c ????????????????????????????????? ????????????????????????????????? thermal characteristics ????????????????????? ????????????????????? characteristic ????? ????? symbol ?????? ?????? max ???? ???? unit ????????????????????? ????????????????????? thermal resistance, junction to case ????? ????? r q jc ?????? ?????? 1.0 ???? ???? c/w ????????????????????? ????????????????????? maximum lead temperature for soldering purposes 1/8 from case for 5 seconds ????? ????? t l ?????? ?????? 275 ???? ???? c (1) pulse test: pulse width = 5 ms, duty cycle 10%. (1) similar device types available with lower v ceo ratings, see the mj13330 (200 v) and mj13331 (250 v). on semiconductor ? semiconductor components industries, llc, 2001 march, 2001 rev. 3 1 publication order number: mj13333/d 20 ampere npn silicon power transistors 400500 volts 175 watts mj13333 case 107 to204aa (to3)
mj13333 http://onsemi.com 2 ????????????????????????????????? ????????????????????????????????? electrical characteristics (t c = 25 c unless otherwise noted) ??????????????????? ??????????????????? characteristic ????? ????? symbol ??? ??? min ???? ???? typ ???? ???? max ??? ??? unit ????????????????????????????????? ????????????????????????????????? off characteristics ??????????????????? ? ????????????????? ? ??????????????????? collectoremitter sustaining voltage (table 1) (i c = 100 ma, i b = 0) ????? ? ??? ? ????? v ceo(sus) ??? ? ? ? ??? 400 ???? ? ?? ? ???? e ???? ? ?? ? ???? e ??? ? ? ? ??? vdc ??????????????????? ? ????????????????? ? ??????????????????? collector cutoff current (v cev = rated value, v be(off) = 1.5 vdc) (v cev = rated value, v be(off) = 1.5 vdc, t c = 150 c) ????? ? ??? ? ????? i cev ??? ? ? ? ??? e e ???? ? ?? ? ???? e e ???? ? ?? ? ???? 0.25 5.0 ??? ? ? ? ??? madc ??????????????????? ? ????????????????? ? ??????????????????? collector cutoff current (v ce = rated v cev , r be = 50 w , t c = 100 c) ????? ? ??? ? ????? i cer ??? ? ? ? ??? e ???? ? ?? ? ???? e ???? ? ?? ? ???? 5.0 ??? ? ? ? ??? madc ??????????????????? ??????????????????? emitter cutoff current (v eb = 6.0 vdc, i c = 0) ????? ????? i ebo ??? ??? e ???? ???? e ???? ???? 1.0 ??? ??? madc ????????????????????????????????? ????????????????????????????????? second breakdown ??????????????????? ??????????????????? second breakdown collector current with base forward biased ????? ????? i s/b ??????????? ??????????? see figure 12 ??????????????????? ??????????????????? clamped inductive soa with base reverse biased ????? ????? rbsoa ??????????? ??????????? see figure 13 ????????????????????????????????? ????????????????????????????????? on characteristics (1) ??????????????????? ? ????????????????? ? ??????????????????? dc current gain (i c = 5.0 adc, v ce = 5.0 vdc) ????? ? ??? ? ????? h fe ??? ? ? ? ??? 10 ???? ? ?? ? ???? e ???? ? ?? ? ???? 60 ??? ? ? ? ??? e ??????????????????? ? ????????????????? ? ? ????????????????? ? ??????????????????? collectoremitter saturation voltage (i c = 10 adc, i b = 2.0 adc) (i c = 20 adc, i b = 6.7 adc) (i c = 10 adc, i b = 2.0 adc, t c = 100 c) ????? ? ??? ? ? ??? ? ????? v ce(sat) ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 1.8 5.0 2.4 ??? ? ? ? ? ? ? ??? vdc ??????????????????? ? ????????????????? ? ??????????????????? base emitter saturation voltage (i c = 10 adc, i b = 2.0 adc) (i c = 10 adc, i b = 2.0 adc, t c = 100 c) ????? ? ??? ? ????? v be(sat) ??? ? ? ? ??? e e ???? ? ?? ? ???? e e ???? ? ?? ? ???? 1.8 1.8 ??? ? ? ? ??? vdc ????????????????????????????????? ????????????????????????????????? dynamic characteristics ??????????????????? ? ????????????????? ? ??????????????????? output capacitance (v cb = 10 vdc, i e = 0, f test = 1.0 khz) ????? ? ??? ? ????? c ob ??? ? ? ? ??? 125 ???? ? ?? ? ???? e ???? ? ?? ? ???? 500 ??? ? ? ? ??? pf ????????????????????????????????? ????????????????????????????????? switching characteristics ????????????????????????????????? ????????????????????????????????? resistive load (table 1) ???????? ???????? delay time ???????????? ???????????? ????? ????? t d ??? ??? e ???? ???? 0.02 ???? ???? 0.1 ??? ??? m s ???????? ???????? rise time ???????????? ???????????? (v cc = 250 vdc, i c = 10 a, i b1 =20a v be( ff) =50vdc t =10 m s ????? ????? t r ??? ??? e ???? ???? 0.3 ???? ???? 0.7 ??? ??? m s ???????? ???????? storage time ???????????? ???????????? i b1 = 2.0 a, v be(off) = 5.0 vdc, t p = 10 m s, duty cycle 2.0%) ????? ????? t s ??? ??? e ???? ???? 1.6 ???? ???? 4.0 ??? ??? m s ???????? ???????? fall time ???????????? ???????????? duty cycle 2.0%) ????? ????? t f ??? ??? e ???? ???? 0.3 ???? ???? 0.7 ??? ??? m s ????????????????????????????????? ????????????????????????????????? inductive load, clamped (table 1) ???????? ???????? storage time ???????????? ???????????? (i c = 10 a(pk), v clamp = 250 vdc, i b1 = 2.0 a, ????? ????? t sv ??? ??? e ???? ???? 2.5 ???? ???? 5.0 ??? ??? m s ???????? ???????? crossover time ???????????? ???????????? (i c 10 a( k) , v clam 250 vdc , i b1 2 . 0 a , v be(off) = 5 vdc, t c = 100 c) ????? ????? t c ??? ??? e ???? ???? 0.8 ???? ???? 2.0 ??? ??? m s ???????? ???????? storage time ???????????? ???????????? (i 10 a( k) v 250 vd i 20a ????? ????? t sv ??? ??? e ???? ???? 1.8 ???? ???? e ??? ??? m s ???????? ???????? crossover time ???????????? ???????????? (i c = 10 a(pk), v clamp = 250 vdc, i b1 = 2.0 a, v be(off) = 5 vdc , t c = 25 c ) ????? ????? t c ??? ??? e ???? ???? 0.4 ???? ???? e ??? ??? m s ???????? ???????? fall time ???????????? ???????????? v be(off) = 5 vdc , t c = 25 c) ????? ????? t fi ??? ??? e ???? ???? 0.2 ???? ???? e ??? ??? m s (1) pulse test: pw = 300 m s, duty cycle 2%.
mj13333 http://onsemi.com 3 , collector current (a) m i c v ce , collector-emitter voltage (volts) v ce , collector-emitter voltage (volts) 0.2 0.2 i c , collector current (amp) 1.2 0 0.8 i c , collector current (amp) 0.4 100 figure 1. dc current gain i c , collector current (amps) 5.0 0.2 0.5 1.0 2.0 20 50 20 figure 2. collector saturation region 0.01 i b , base current (amp) 0 1.6 0.8 0.4 h fe , dc current gain 10 t j = 150 c figure 3. collectoremitter saturation region 1.0 5.0 0.5 figure 4. baseemitter voltage figure 5. collector cutoff region 2.0 1.2 -0.4 figure 6. capacitance v be , base-emitter voltage (volts) 10 -1 -0.2 0 +0.2 +0.4 +0.6 3000 0.1 v r , reverse voltage (volts) 30 10 1000 10 0 100 1000 100 forward v ce = 250 v 10 a 1 a reverse 10 1 10 2 10 3 10 4 c ib v ce = 5 v 25 c 5.0 10 0.02 0.5 1.0 2.0 10 5.0 0.1 0.2 0.05 500 0.5 1.0 5.0 50 50 200 700 2000 1.6 i c /i b = 5 2.0 20 2.0 1.2 0 0.8 0.4 1.6 150 c 10 1.0 5.0 0.5 2.0 20 10 500 5 a 150 c 25 c v be(sat) , base-emitter saturation voltage (volts) 2.0 i c /i b = 5 25 c 150 c 125 c 100 c 75 c 25 c c, capacitance (pf) c ob
mj13333 http://onsemi.com 4 v be(off) , reverse base voltage (volts) figure 7. inductive switching measurements figure 8. reverse base current versus v be ( off ) with no external base resistance 2.0 5.0 10 10 7.0 2.0 , base current (amp) i b2(pk) 0 i c = 10 a i b1 = 2 a v clamp = 250 v t j = 25 c 5.0 t rv time i c v ce 90% i b1 t sv i c pk v clamp 90% v clamp 90% i c 10% v clamp 10% i c pk 2% i c i b t fi t ti t c switching times note in resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. however, for inductive loads which are common to switchmode power supplies and hammer drivers, current and voltage waveforms are not in phase. therefore, separate measurements must be made on each waveform to determine the total switching time. for this reason, the following new terms have been defined. t sv = voltage storage time, 90% i b1 to 10% v clamp t rv = voltage rise time, 10 90% v clamp t fi = current fall time, 90 10% i c t ti = current tail, 10 2% i c t c = crossover time, 10% v clamp to 10% i c an enlarged portion of the inductive switching waveforms is shown in figure 7 to aid in the visual identity of these terms. for the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from an222: p swt = 1/2 v cc i c (t c )f in general, t rv + t fi t c . however, at lower test currents this relationship may not be valid. as is common with most switching transistors, resistive switching is specified at 25 c and has become a benchmark for designers, however, for designers of high frequency converter circuits, the user oriented specifications which make this a aswitchmodeo transistor are the inductive switching speeds (t c and t sv ) which are guaranteed at 100 c. 20 figure 9. turnon switching times i c , collector current (amp) 0.2 0.5 0.02 figure 10. turnoff switching times 2.0 1.0 0.1 0.05 20 i c , collector current (amp) 1.0 0.05 5.0 2.0 1.0 t, time (s) m 0.5 5.0 2.0 10 t, time (s) m 0.5 0.2 0.2 v cc = 250 v i c /i b = 5 v ce = 250 v i c /i b = 5 v be(off) = 5 v t r t d 0.2 0.5 1.0 5.0 2.0 10 0.1 t s t f resistive switching performance
mj13333 http://onsemi.com 5 table 1. test conditions for dynamic performance v ceo(sus) rbsoa and inductive switching resistive switching input conditions circuit values test circuits 20 1 0 pw varied to attain i c = 100 ma l coil = 80 mh, v cc = 10 v r coil = 0.7 w l coil = 180 m h r coil = 0.05 w v cc = 20 v v cc = 250 v r l = 50 w pulse width = 10 m s inductive test circuit turnon time i b1 adjusted to obtain the forced h fe desired turnoff time use inductive switching driver as the input to the resistive test circuit. t 1 adjusted to obtain i c test equipment scope e tektronix 475 or equivalent resistive test circuit output waveforms 2 i b1 1 2 v clamp = 250 v r b adjusted to attain desired i b1 +10 v 250 m f 15 v 0 50 w 100 w 330 w 430 w 39 w 250 m f -5.2 1 2 r2 5.1 w 5 w 47 w 470 w 2 w +15 v r1 all diodes e 1n4934 all npn e mje200 all pnp e mje210 adjust r1 to obtain i b1 for switching and rbsoa, r2 = 0 for v ceo(sus) , r2 = 1 input 2 r coil l coil v cc v clamp rs = 0.1 w 1n4937 or equivalent tut see above for detailed conditions t 1 i c v ce i c(pk) t f clamped t f t t t 2 time v ce or v clamp 1 2 tut r l v cc t 1 l coil (i c pk ) v cc t 2 l coil (i c pk ) v clamp t, time (ms) 1 0.01 0.01 0.5 0.2 0.1 0.05 0.02 r(t), effective transient thermal 0.05 1 2 3 10 20 50 100 200 300 r q jc (t) = r(t) r q jc r q jc = 1.0 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 d = 0.5 0.2 0.05 0.02 0.01 single pulse 0.1 0.1 0.5 0.2 resistance (normalized) 500 1000 0.7 0.3 0.07 0.03 0.02 0.03 0.3 5 30 figure 11. thermal response
mj13333 http://onsemi.com 6 i c(pk) , peak collector current (amps) 0.005 figure 12. forward bias safe operating area 6 v ce , collector-emitter voltage (volts) 10 50 50 10 2 1 5 0.2 450 20 100 figure 13. rbsoa, reverse bias switching safe operating area v ce , collector-emitter voltage (volts) 0 100 200 16 8.0 20 300 i c /i b 5 v be(off) = 5 v t j = 100 c i c , collector current (amp) 0.05 200 350 12 4.0 0.1 0.02 400 500 dc 1 ms 10 m s 100 m s 400 500 600 600 20 0.01 mj13333 bonding wire limit thermal limit @ t c = 25 c (single pulse) second breakdown limit safe operating area information forward bias there are two limitations on the power handling ability of a transistor average junction temperature and second breakdown. safe operating area curves indicate i c v ce limits of the transistor that must be observed for reliable operation, i.e., the transistor must not be subjected to greater dissipation than the curves indicate. the data of figure 12 is based on t c = 25 c. t j(pk) is variable depending on power level. second breakdown pulse limits are valid for duty cycles to 10% but must be derated when t c 25 c. second breakdown limitations do not derate the same as thermal limitations. allowable current at the voltages shown on figure 12 may be found at any case temperature by using the appropriate curve on figure 14. t j(pk) may be calculated from the data in figure 11. at high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. reverse bias for inductive loads, high voltage and high current must be sustained simultaneously during turnoff, in most cases, with the base to emitter junction reverse biased. under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. this can be accomplished by several means such as active clamping, rc snubbing, load line shaping, etc. the safe level for these devices is specified as reverse bias safe operating area and represents the voltagecurrent condition allowable during reverse biased turnoff. this rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. figure 13 gives the complete rbsoa characteristics. 0 figure 14. power derating t c , case temperature ( c) 0 40 80 80 40 100 120 power derating factor (%) 160 200 60 20 thermal derating forward bias second breakdown derating
mj13333 http://onsemi.com 7 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. all rules and notes associated with referenced to-204aa outline shall apply. style 1: pin 1. base 2. emitter case: collector dim min max min max millimeters inches a 1.550 ref 39.37 ref b --- 1.050 --- 26.67 c 0.250 0.335 6.35 8.51 d 0.038 0.043 0.97 1.09 e 0.055 0.070 1.40 1.77 g 0.430 bsc 10.92 bsc h 0.215 bsc 5.46 bsc k 0.440 0.480 11.18 12.19 l 0.665 bsc 16.89 bsc n --- 0.830 --- 21.08 q 0.151 0.165 3.84 4.19 u 1.187 bsc 30.15 bsc v 0.131 0.188 3.33 4.77 a n e c k t seating plane 2 pl d m q m 0.13 (0.005) y m t m y m 0.13 (0.005) t q y 2 1 u l g b v h case 107 to204aa (to3) issue z
mj13333 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mj13333/d switchmode is a trademark of semiconductor components industries, llc. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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